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1. general description the lpc2101/2102/2103 microcontrollers are based on a 16-bit/32-bit arm7tdmi-s cpu with real-time emulation that combines the microcontroller with 8 kb, 16 kb or 32 kb of embedded high-speed ?ash memory. a 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. for critical performance in interrupt service routines and dsp algorithms, this increases performance up to 30 % over thumb mode. for critical code size applications, the alternative 16-bit thumb mode reduces code by more than 30 % with minimal performance penalty. due to their tiny size and low power consumption, the lpc2101/2102/2103 are ideal for applications where miniaturization is a key requirement. a blend of serial communications interfaces ranging from multiple uarts, spi to ssp and two i 2 c-buses, combined with on-chip sram of 2 kb/4 kb/8 kb, make these devices very well suited for communication gateways and protocol converters. the superior performance also makes these devices suitable for use as math coprocessors. various 32-bit and 16-bit timers, an improved 10-bit adc, pwm features through output match on all timers, and 32 fast gpio lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. features 2.1 key features n 16-bit/32-bit arm7tdmi-s microcontroller in a tiny lqfp48 package. n 2 kb/4 kb/8 kb of on-chip static ram and 8 kb/16 kb/32 kb of on-chip ?ash program memory. 128-bit wide interface/accelerator enables high-speed 70 mhz operation. n isp/iap via on-chip bootloader software. single ?ash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms. n embeddedice rt offers real-time debugging with the on-chip realmonitor software. n the 10-bit a/d converter provides eight analog inputs, with conversion times as low as 2.44 m s per channel and dedicated result registers to minimize interrupt overhead. n two 32-bit timers/external event counters with combined seven capture and seven compare channels. n two 16-bit timers/external event counters with combined three capture and seven compare channels. n low power real-time clock (rtc) with independent power and dedicated 32 khz clock input. n multiple serial interfaces including two uarts (16c550), two fast i 2 c-buses (400 kbit/s), spi and ssp with buffering and variable data length capabilities. lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers; 8 kb/16 kb/32 kb ?ash with isp/iap, fast ports and 10-bit adc rev. 01 18 january 2006 preliminary data sheet
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 2 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers n vectored interrupt controller with con?gurable priorities and vector addresses. n up to thirty-two 5 v tolerant fast general purpose i/o pins. n up to 13 edge or level sensitive external interrupt pins available. n 70 mhz maximum cpu clock available from programmable on-chip pll with a possible input frequency of 10 mhz to 25 mhz and a settling time of 100 m s. n on-chip integrated oscillator operates with an external crystal in the range from 1 mhz to 25 mhz. n power saving modes include idle mode, power-down mode with rtc active, and power-down mode. n individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization. n processor wake-up from power-down mode via external interrupt or rtc. 3. ordering information 3.1 ordering options table 1: ordering information type number package name description version lpc2101fbd48 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 lpc2102fbd48 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 lpc2103fbd48 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 LPC2103FA44 plcc44 plastic leaded chip carrier; 44 leads sot187-2 table 2: ordering options type number flash memory ram adc temperature range ( c) lpc2101fbd48 8 kb 2 kb 8 inputs - 40 to +85 lpc2102fbd48 16 kb 4 kb 8 inputs - 40 to +85 lpc2103fbd48 32 kb 8 kb 8 inputs - 40 to +85 LPC2103FA44 32 kb 8 kb 8 inputs - 40 to +85
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 3 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 4. block diagram (1) pins shared with gpio. fig 1. block diagram 002aab814 system clock trst tms tck tdi tdo xtal2 v dd(3v3) xtal1 amba ahb (advanced high-performance bus) memory accelerator ahb bridge test/debug interface ahb to apb bridge vectored interrupt controller system functions pll 8 kb/16 kb/ 32 kb flash arm7tdmi-s lpc2101/2102/2103 internal sram controller 2 kb/4 kb/ 8 kb sram arm7 local bus apb (arm peripheral bus) scl0, scl1 (1) sda0, sda1 (1) 3 cap0 (1) 4 cap1 (1) 3 cap2 (1) 3 mat0 (1) 4 mat1 (1) 3 mat2 (1) 4 mat3 (1) ad0[7:0] i 2 c-bus serial interfaces 0 and 1 capture/compare external counter timer 0/timer 1/ timer 2/timer 3 eint2 to eint0 (1) external interrupts sck0, sck1 (1) mosi0, mosi1 (1) miso0, miso1 (1) ssel0, ssel1 (1) spi and ssp serial interfaces adc txd0, txd1 (1) rxd0, rxd1 (1) uart0/uart1 rtxc2 rtxc1 vbat real-time clock watchdog timer system control p0[31:0] p0[31:0] general purpose i/o high speed general purpose i/o rst v ss 8 kb boot rom v dd(1v8) dsr1, cts1, rts1, dtr1 dcd1, ri1
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 4 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 5. pinning information 5.1 pinning fig 2. lqfp48 pin con?guration lpc2101/2102/2103 p0.19/mat1.2/miso1 p0.11/cts1/cap1.1/ad0.4 p0.20/mat1.3/mosi1 p0.10/rts1/cap1.0/ad0.3 p0.21/ssel1/mat3.0 p0.24/ad0.2 vbat p0.23/ad0.1 v dd(1v8) p0.22/ad0.0 rst v ssa v ss p0.9/rxd1/mat2.2 p0.27/trst/cap2.0 p0.8/txd1/mat2.1 p0.28/tms/cap2.1 p0.7/ssel0/mat2.0 p0.29/tck/cap2.2 dbgsel x1 rtck x2 rtxc2 p0.0/txd0/mat3.1 p0.18/cap1.3/sda1 p0.1/rxd0/mat3.2 p0.17/cap1.2/scl1 p0.30/tdi/mat3.3 p0.16/eint0/mat0.2 p0.31/tdo p0.15/ri1/eint2 v dd(3v3) p0.14/dcd1/sck1/eint1 p0.2/scl0/cap0.0 v ss v ss v dda rtxc1 p0.13/dtr1/mat1.1 p0.3/sda0/mat0.0 v dd(3v3) p0.4/sck0/cap0.1 p0.26/ad0.7 p0.5/miso0/mat0.1 p0.6/mosi0/cap0.2 p0.25/ad0.6 p0.12/dsr1/mat1.0/ad0.5 002aab821 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 5 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers fig 3. plcc44 pin con?guration lpc2101/2102/2103 002aab920 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 p0.27/trst/cap2.0 v ss p0.28/tms/cap2.1 v dda p0.29/tck/cap2.2 p0.13/dtr1/mat1.1 x1 v dd(3v3) x2 p0.25/ad0.6 p0.0/txd0/mat3.1 p0.12/dsr1/mat1.0/ad0.5 p0.1/rxd0/mat3.2 p0.11/cts1/cap1.1/ad0.4 p0.30/tdi/mat3.3 p0.10/rts1/cap1.0/ad0.3 p0.31/tdo p0.24/ad0.2 p0.2/scl0/cap0.0 p0.23/ad0.1 v ss p0.22/ad0.0 rtxc1 v ss p0.3/sda0/mat0.0 rst p0.4/sck0/cap0.1 v dd(1v8) p0.5/miso0/mat0.1 p0.21/ssel1/mat3.0 p0.6/mosi0/cap0.2 p0.20/mat1.3/mosi1 rtxc2 p0.19/mat1.2/miso1 dbgsel p0.18/cap1.3/sda1 p0.7/ssel0/mat2.0 p0.17/cap1.2/scl1 p0.8/txd1/mat2.1 p0.16/eint0/mat0.2 p0.9/rxd1/mat2.2 p0.15/ri1/eint2 v ssa p0.14/dcd1/sck1/eint1
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 6 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 5.2 pin description table 3: pin description symbol lqfp48 plcc44 type description p0.0 to p0.31 i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. a total of 31 pins of the port 0 can be used as general purpose bidirectional digital i/os while p0.31 is an output only pin. the operation of port 0 pins depends upon the pin function selected via the pin connect block. p0.0/txd0/ mat3.1 13 [1] 18 [1] i/o p0.0 general purpose input/output digital pin (gpio). o txd0 transmitter output for uart0. o mat3.1 pwm output 1 for timer 3. p0.1/rxd0/ mat3.2 14 [2] 19 [2] i/o p0.1 general purpose input/output digital pin (gpio). i rxd0 receiver input for uart0. o mat3.2 pwm output 2 for timer 3. p0.2/scl0/ cap0.0 18 [3] 22 [3] i/o p0.2 general purpose input/output digital pin (gpio). i/o scl0 i 2 c0 clock input/output. open-drain output (for i 2 c-bus compliance). i cap0.0 capture input for timer 0, channel 0. p0.3/sda0/ mat0.0 21 [3] 25 [3] i/o p0.3 general purpose input/output digital pin (gpio). i/o sda0 i 2 c0 data input/output. open-drain output (for i 2 c-bus compliance). o mat0.0 pwm output for timer 0, channel 0. p0.4/sck0/ cap0.1 22 [4] 26 [4] i/o p0.4 general purpose input/output digital pin (gpio). i/o sck0 serial clock for spi0. spi clock output from master or input to slave. i cap0.1 capture input for timer 0, channel 1. p0.5/miso0/ mat0.1 23 [4] 27 [4] i/o p0.5 general purpose input/output digital pin (gpio). i/o miso0 master in slave out for spi0. data input to spi master or data output from spi slave. o mat0.1 pwm output for timer 0, channel 1. p0.6/mosi0/ cap0.2 24 [4] 28 [4] i/o p0.6 general purpose input/output digital pin (gpio). i/o mosi0 master out slave in for spi0. data output from spi master or data input to spi slave. i cap0.2 capture input for timer 0, channel 2. p0.7/ssel0/ mat2.0 28 [2] 31 [2] i/o p0.7 general purpose input/output digital pin (gpio). i ssel0 slave select for spi0. selects the spi interface as a slave. o mat2.0 pwm output for timer 2, channel 0. p0.8/txd1/ mat2.1 29 [4] 32 [4] i/o p0.8 general purpose input/output digital pin (gpio). o txd1 transmitter output for uart1. o mat2.1 pwm output for timer 2, channel 1. p0.9/rxd1/ mat2.2 30 [2] 33 [2] i/o p0.9 general purpose input/output digital pin (gpio). i rxd1 receiver input for uart1. o mat2.2 pwm output for timer 2, channel 2.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 7 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers p0.10/rts1/ cap1.0/ad0.3 35 [4] 38 [4] i/o p0.10 general purpose input/output digital pin (gpio). o rts1 request to send output for uart1. i cap1.0 capture input for timer 1, channel 0. i ad0.3 adc 0, input 3. p0.11/cts1/ cap1.1/ad0.4 36 [3] 39 [3] i/o p0.11 general purpose input/output digital pin (gpio). i cts1 clear to send input for uart1. i cap1.1 capture input for timer 1, channel 1. i ad0.4 adc 0, input 4. p0.12/dsr1/ mat1.0/ad0.5 37 [4] 40 [4] i/o p0.12 general purpose input/output digital pin (gpio). i dsr1 data set ready input for uart1. o mat1.0 pwm output for timer 1, channel 0. i ad0.5 adc 0, input 5. p0.13/dtr1/ mat1.1 41 [4] 43 [4] i/o p0.13 general purpose input/output digital pin (gpio). o dtr1 data terminal ready output for uart1. o mat1.1 pwm output for timer 1, channel 1. p0.14/dcd1/ sck1/eint1 44 [3] 2 [3] i/o p0.14 general purpose input/output digital pin (gpio). i dcd1 data carrier detect input for uart1. i/o sck1 serial clock for spi1. spi clock output from master or input to slave. i eint1 external interrupt 1 input. p0.15/ri1/ eint2 45 [4] 3 [4] i/o p0.15 general purpose input/output digital pin (gpio). i ri1 ring indicator input for uart1. i eint2 external interrupt 2 input. p0.16/eint0/ mat0.2 46 [2] 4 [2] i/o p0.16 general purpose input/output digital pin (gpio). i eint0 external interrupt 0 input. o mat0.2 pwm output for timer 0, channel 2. p0.17/cap1.2/ scl1 47 [1] 5 [1] i/o p0.17 general purpose input/output digital pin (gpio). i cap1.2 capture input for timer 1, channel 2. i/o scl1 i 2 c1 clock input/output. open-drain output (for i 2 c-bus compliance). p0.18/cap1.3/ sda1 48 [1] 6 [1] i/o p0.18 general purpose input/output digital pin (gpio). i cap1.3 capture input for timer 1, channel 3. i/o sda1 i 2 c1 data input/output. open-drain output (for i 2 c-bus compliance). p0.19/mat1.2/ miso1 1 [1] 7 [1] i/o p0.19 general purpose input/output digital pin (gpio). o mat1.2 pwm output for timer 1, channel 2. i/o miso1 master in slave out for ssp. data input to spi master or data output from ssp slave. p0.20/mat1.3/ mosi1 2 [2] 8 [2] i/o p0.20 general purpose input/output digital pin (gpio). o mat1.3 pwm output for timer 1, channel 3. i/o mosi1 master out slave for ssp. data output from ssp master or data input to ssp slave. table 3: pin description continued symbol lqfp48 plcc44 type description
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 8 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers p0.21/ssel1/ mat3.0 3 [4] 9 [4] i/o p0.21 general purpose input/output digital pin (gpio). i ssel1 slave select for spi1. selects the spi interface as a slave. o mat3.0 pwm output for timer 3, channel 0. p0.22/ad0.0 32 [4] 35 [4] i/o p0.22 general purpose input/output digital pin (gpio). i ad0.0 adc 0, input 0. p0.23/ad0.1 33 [1] 36 [1] i/o p0.23 general purpose input/output digital pin (gpio). i ad0.1 adc 0, input 1. p0.24/ad0.2 34 [1] 37 [1] i/o p0.24 general purpose input/output digital pin (gpio). i ad0.2 adc 0, input 2. p0.25/ad0.6 38 [1] 41 [1] i/o p0.25 general purpose input/output digital pin (gpio). i ad0.6 adc 0, input 6. p0.26/ad0.7 39 [1] n.c. i/o p0.26 general purpose input/output digital pin (gpio). i ad0.7 adc 0, input 7. p0.27/trst/ cap2.0 8 [4] 13 [4] i/o p0.27 general purpose input/output digital pin (gpio). i trst test reset for jtag interface. i cap2.0 capture input for timer 2, channel 0. p0.28/tms/ cap2.1 9 [4] 14 [4] i/o p0.28 general purpose input/output digital pin (gpio). i tms test mode select for jtag interface. i cap2.1 capture input for timer 2, channel 1. p0.29/tck/ cap2.2 10 [4] 15 [4] i/o p0.29 general purpose input/output digital pin (gpio). i tck test clock for jtag interface. i cap2.2 capture input for timer 2, channel 2. p0.30/tdi/ mat3.3 15 [4] 20 [4] i/o p0.30 general purpose input/output digital pin (gpio). i tdi test data in for jtag interface. o mat3.3 pwm output 3 for timer 3. p0.31/tdo 16 [4] 21 [4] o p0.31 general purpose output only digital pin (gpio). o tdo test data out for jtag interface. rtxc1 20 [5] 24 [5] i input to the rtc oscillator circuit. rtxc2 25 [5] 29 [5] o output from the rtc oscillator circuit. rtck 26 [5] n.c. i/o returned test clock output: extra signal added to the jtag port. assists debugger synchronization when processor frequency varies. bidirectional pin with internal pull-up. x1 11 16 i input to the oscillator circuit and internal clock generator circuits. x2 12 17 o output from the oscillator ampli?er. dbgsel 27 30 i debug select: when low, the part operates normally. when high, debug mode is entered. input with internal pull-down. rst 6 11 i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. v ss 7, 19, 43 1, 12, 23 i ground: 0 v reference. table 3: pin description continued symbol lqfp48 plcc44 type description
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 9 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. [2] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. [3] open-drain 5 v tolerant digital i/o i 2 c-bus 400 khz speci?cation compatible pad. it requires external pull-up to provide an output functionality. [4] 5 v tolerant pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog input function. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. when con?gured as an adc in put, digital section of the pad is disabled. [5] pad provides special analog functionality. v ssa 31 34 i analog ground: 0 v reference. this should be nominally the same voltage as v ss but should be isolated to minimize noise and error. v dda 42 44 i analog 3.3 v power supply: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the on-chip pll. this pin also provides a voltage reference level for the adc. v dd(1v8) 510i 1.8 v core power supply: this is the power supply voltage for internal circuitry. v dd(3v3) 17, 40 42 i 3.3 v pad power supply: this is the power supply voltage for the i/o ports. vbat 4 n.c. i rtc power supply: 3.3 v on this pin supplies the power to the rtc. table 3: pin description continued symbol lqfp48 plcc44 type description
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 10 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 6. functional description 6.1 architectural overview the arm7tdmi-s is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. the arm architecture is based on reduced instruction set computer (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers (cisc). this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set. ? a 16-bit thumb set. the thumb sets 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arms performance advantage over a traditional 16-bit processor using 16-bit registers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm processor connected to a 16-bit memory system. the particular ?ash implementation in the lpc2101/2102/2103 allows for full speed execution also in arm mode. it is recommended to program performance critical and short code sections in arm mode. the impact on the overall code size will be minimal but the speed can be increased by 30 % over thumb mode. 6.2 on-chip ?ash program memory the lpc2101/2102/2103 incorporate a 8 kb, 16 kb or 32 kb ?ash memory system respectively. this memory may be used for both code and data storage. programming of the ?ash memory may be accomplished in several ways. it may be programmed in system via the serial port. the application program may also erase and/or program the ?ash while the application is running, allowing a great degree of ?exibility for data storage ?eld ?rmware upgrades, etc. the entire ?ash memory is available for user code as the bootloader resides in a separate memory. the lpc2101/2102/2103 ?ash memory provides a minimum of 100,000 erase/write cycles and 20 years of data-retention memory.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 11 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 6.3 on-chip static ram on-chip static ram may be used for code and/or data storage. the sram may be accessed as 8-bits, 16-bits, and 32-bits. the lpc2101/2102/2103 provide 2 kb, 4 kb or 8 kb of static ram. 6.4 memory map the lpc2101/2102/2103 memory map incorporates several distinct regions, as shown in figure 4 . in addition, the cpu interrupt vectors may be re-mapped to allow them to reside in either ?ash memory (the default) or on-chip static ram. this is described in section 6.17 system control . fig 4. lpc2101/2102/2103 memory map ahb peripherals apb peripherals reserved address space reserved address space boot block reserved address space 8 kb on-chip static ram (lpc2103) 2 kb on-chip static ram (lpc2101) 32 kb on-chip non-volatile memory (lpc2103) 0xffff ffff 0xf000 0000 0xe000 0000 0xc000 0000 0x8000 0000 0x7fff ffff 0x4000 1000 0x4000 07ff 0x4000 2000 0x4000 1fff 4 kb on-chip static ram (lpc2102) 0x4000 0800 0x4000 0fff 0x7fff e000 0x7fff dfff 0x4000 0000 0x0000 8000 0x0000 7fff 0x0000 4000 4.0 gb 3.75 gb 3.5 gb 3.0 gb 2.0 gb 1.0 gb 16 kb on-chip non-volatile memory (lpc2102) 0x0000 3fff 0x0000 2000 8 kb on-chip non-volatile memory (lpc2101) 0x0000 1fff 0x0000 0000 0.0 gb 002aab822
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 12 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 6.5 interrupt controller the vic accepts all of the interrupt request inputs and categorizes them as fiq, vectored irq, and non-vectored irq as de?ned by programmable settings. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fiq has the highest priority. if more than one request is assigned to fiq, the vic combines the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classi?ed as fiq, because then the fiq service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. if more than one request is assigned to the fiq class, the fiq service routine will read a word from the vic that identi?es which fiq source(s) is (are) requesting an interrupt. vectored irqs have the middle priority. sixteen of the interrupt requests can be assigned to this category. any of the interrupt requests can be assigned to any of the 16 vectored irq slots, among which slot 0 has the highest priority and slot 15 has the lowest. non-vectored irqs have the lowest priority. the vic combines the requests from all the vectored and non-vectored irqs to produce the irq signal to the arm processor. the irq service routine can start by reading a register from the vic and jumping there. if any of the vectored irqs are pending, the vic provides the address of the highest-priority requesting irqs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored irqs. the default routine can read another vic register to see what irqs are active. 6.5.1 interrupt sources each peripheral device has one interrupt line connected to the vectored interrupt controller, but may have several internal interrupt ?ags. individual interrupt ?ags may also represent more than one interrupt source. 6.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. con?guration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned. the pin control module with its pin select registers de?nes the functionality of the microcontroller in a given hardware environment. after reset all pins of port 0 are con?gured as input with the following exceptions: if debug is enabled, the jtag pins will assume their jtag functionality. the pins associated with the i 2 c0 interface are open-drain.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 13 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 6.7 fast general purpose parallel i/o device pins that are not connected to a speci?c peripheral function are controlled by the gpio registers. pins may be dynamically con?gured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back, as well as the current state of the port pins. lpc2101/2102/2103 introduce accelerated gpio functions over prior lpc2000 devices: ? gpio registers are relocated to the arm local bus for the fastest possible i/o timing. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte addressable. ? entire port value can be written in one instruction. 6.7.1 features ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? direction control of individual bits. ? separate control of output set and clear. ? all i/o default to inputs after reset. 6.8 10-bit a/d converter the lpc2101/2102/2103 contain one analog to digital converter. it is a single 10-bit successive approximation analog to digital converter with eight channels. 6.8.1 features ? measurement range of 0 v to 3.3 v. ? each converter capable of performing more than 400,000 10-bit samples per second. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on input pin or timer match signal. ? every analog input has a dedicated result register to reduce interrupt overhead. 6.9 uarts the lpc2101/2102/2103 each contain two uarts. in addition to standard transmit and receive data lines, uart1 also provides a full modem control handshake interface. compared to previous lpc2000 microcontrollers, uarts in lpc2101/2102/2103 include a fractional baud rate generator for both uarts. standard baud rates such as 115200 can be achieved with any crystal frequency above 2 mhz. 6.9.1 features ? 16 byte receive and transmit fifos. ? register locations conform to 550 industry standard. ? receiver fifo trigger points at 1, 4, 8, and 14 bytes
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 14 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers ? built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ? transmission fifo control enables implementation of software (xon/xoff) ?ow control on both uarts. ? uart1 is equipped with standard modem interface signals. this module also provides full support for hardware ?ow control (auto-cts/rts). 6.10 i 2 c-bus serial i/o controllers the lpc2101/2102/2103 each contain two i 2 c-bus controllers. the i 2 c-bus is bidirectional, for inter-ic control using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., lcd driver) or a transmitter with the capability to both receive and send information such as serial memory. transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in lpc2101/2102/2103 supports bit rates up to 400 kbit/s (fast i 2 c). 6.10.1 features ? compliant with standard i 2 c-bus interface. ? easy to con?gure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can also be used for test and diagnostic purposes. 6.11 spi serial i/o controller the lpc2101/2102/2103 each contain one spi controller. the spi is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 6.11.1 features ? compliant with spi speci?cation. ? synchronous, serial, full duplex, communication.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 15 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers ? combined spi master and slave. ? maximum data bit rate of one eighth of the input clock rate. 6.12 ssp serial i/o controller the lpc2101/2102/2103 each contain one ssp. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. however, only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with data frames of 4 bits to 16 bits ?owing from the master to the slave and from the slave to the master. often only one of these data streams carries meaningful data. 6.12.1 features ? compatible with motorola spi, 4-wire tis ssi and national semiconductors microwire buses. ? synchronous serial communication. ? master or slave operation. ? 8-frame fifos for both transmit and receive. ? four bits to 16 bits per frame. 6.13 general purpose 32-bit timers/external event counters the timer/counter is designed to count cycles of the peripheral clock (pclk) or an externally supplied clock and optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. it also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. the lpc2101/2102/2103 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the pclk. in this con?guration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts. 6.13.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? external event counter or timer operation. ? four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? four external outputs per timer/counter corresponding to match registers, with the following capabilities: C set low on match.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 16 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers C set high on match. C toggle on match. C do nothing on match. 6.14 general purpose 16-bit timers/external event counters the timer/counter is designed to count cycles of the peripheral clock (pclk) or an externally supplied clock and optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. it also includes three capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. the lpc2101/2102/2103 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the pclk. in this con?guration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts. 6.14.1 features ? two 16-bit timer/counters with a programmable 16-bit prescaler. ? external event counter or timer operation. ? three 16-bit capture channels that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 16-bit match registers that allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? four external outputs per timer/counter corresponding to match registers, with the following capabilities: C set low on match. C set high on match. C toggle on match. C do nothing on match. 6.15 watchdog timer the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 6.15.1 features ? internally resets chip if not periodically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 17 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal pre-scaler. ? selectable time period from (t pclk 256 4) to (t pclk 2 32 4) in multiples of t pclk 4. 6.16 real-time clock the real-time clock (rtc) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. the rtc has been designed to use little power, making it suitable for battery powered systems where the cpu is not running continuously (idle mode). 6.16.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra-low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? can use either the rtc dedicated 32 khz oscillator input or clock derived from the external crystal/oscillator input at xtal1. programmable reference clock divider allows ?ne adjustment of the rtc. ? dedicated power supply pin can be connected to a battery or the main 3.3 v. 6.17 system control 6.17.1 crystal oscillator on-chip integrated oscillator operates with external crystal in range of 1 mhz to 25 mhz. the oscillator output frequency is called f osc and the arm processor clock frequency is referred to as cclk for purposes of rate equations, etc. f osc and cclk are the same value unless the pll is running and connected. refer to section 6.17.2 pll for additional information. 6.17.2 pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up into the range of 10 mhz to 70 mhz with a current controlled oscillator (cco). the multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the cpu). the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must con?gure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. the pll settling time is 100 m s.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 18 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 6.17.3 reset and wake-up timer reset has two sources on the lpc2101/2102/2103: the reset pin and watchdog reset. the reset pin is a schmitt trigger input pin with an additional glitch ?lter. assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a ?xed number of clocks have passed, and the on-chip ?ash controller has completed its initialization. when the internal reset is removed, the processor begins executing at address 0, which is the reset vector. at that point, all of the processor and peripheral registers have been initialized to predetermined reset values. the wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. this is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. when power is applied to the chip, or some event caused the chip to exit power-down mode, some time is required for the oscillator to produce a signal of suf?cient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 6.17.4 code security this feature of the lpc2101/2102/2103 allow an application to control whether it can be debugged or protected from observation. if after reset on-chip bootloader detects a valid checksum in ?ash and reads 0x8765 4321 from address 0x1fc in ?ash, debugging will be disabled and thus the code in ?ash will be protected from observation. once debugging is disabled, it can only be enabled by performing a full chip erase using the isp. 6.17.5 external interrupt inputs the lpc2101/2102/2103 include up to three edge or level sensitive external interrupt inputs as selectable pin functions. when the pins are combined, external events can be processed as three independent interrupt signals. the external interrupt inputs can optionally be used to wake-up the processor from power-down mode. additionally all 10 capture input pins can also be used as external interrupts without the option to wake the device up from power-down mode. 6.17.6 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. vectors may be mapped to the bottom of the on-chip ?ash memory, or to the on-chip static ram. this allows code running in different memory spaces to have control of the interrupts.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 19 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 6.17.7 power control the lpc2101/2102/2103 supports two reduced power modes: idle mode and power-down mode. in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. in power-down mode, the oscillator is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout power-down mode and the logic levels of chip output pins remain static. the power-down mode can be terminated and normal operation resumed by either a reset or certain speci?c interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, power-down mode reduces chip power consumption to nearly zero. selecting an external 32 khz clock instead of the pclk as a clock-source for the on-chip rtc will enable the microcontroller to have the rtc active during power-down mode. power-down current is increased with rtc active. however, it is signi?cantly lower than in idle mode. a power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and idle mode. 6.17.8 apb bus the apb divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk). the apb divider serves two purposes. the ?rst is to provide peripherals with the desired pclk via apb bus so that they can operate at the speed chosen for the arm processor. in order to achieve this, the apb bus may be slowed down to 1 2 to 1 4 of the processor clock rate. because the apb bus must work properly at power-up (and its timing cannot be altered if it does not work since the apb divider control registers reside on the apb bus), the default condition at reset is for the apb bus to run at 1 4 of the processor clock rate. the second purpose of the apb divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. because the apb divider is connected to the pll output, the pll remains active (if it was running) during idle mode. 6.18 emulation and debugging the lpc2101/2102/2103 support emulation and debugging via a jtag serial port. 6.18.1 embeddedice standard arm embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm core. the arm core has a debug communication channel function built-in. the debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program ?ow or even
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 20 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers entering the debug state. the debug communication channel is accessed as a co-processor 14 by the program running on the arm7tdmi-s core. the debug communication channel allows the jtag port to be used for sending and receiving data without affecting the normal program ?ow. the debug communication channel data and control registers are mapped in to addresses in the embeddedice logic. 6.18.2 realmonitor realmonitor is a con?gurable software module, developed by arm inc., which enables real time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communicates with the host using the dcc, which is present in the embeddedice logic. the lpc2101/2102/2103 contain a speci?c con?guration of realmonitor software programmed into the on-chip boot rom memory.
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 21 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 7. limiting values [1] the following applies to the limiting values: a) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [2] core and internal rail. [3] external rail. [4] on adc related pins. [5] including voltage on outputs in 3-state mode. [6] only valid when the v dd(3v3) supply voltage is present. [7] not to exceed 4.6 v. [8] per supply pin. [9] the peak current is limited to 25 times the corresponding maximum current. [10] per ground pin. [11] dependent on package type. table 4: limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(1v8) supply voltage (1.8 v) [2] - 0.5 +2.5 v v dd(3v3) supply voltage (3.3 v) [3] - 0.5 +3.6 v v dda analog 3.3 v pad supply voltage - 0.5 4.6 v v i(vbat) input voltage on pin vbat for the rtc - 0.5 4.6 v v ia analog input voltage [4] - 0.5 5.1 v v i input voltage 5 v tolerant i/o pins [5] [6] - 0.5 6.0 v other i/o pins [5] - 0.5 v dd + 0.5 [7] v i dd supply current [8] - 100 [9] ma i ss ground current [10] - 100 [9] ma t stg storage temperature [11] - 40 125 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 22 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 8. static characteristics table 5: static characteristics t a = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v dd(1v8) supply voltage (1.8 v) [2] 1.65 1.8 1.95 v v dd(3v3) supply voltage (3.3 v) [3] 3.0 3.3 3.6 v v dda analog 3.3 v pad supply voltage 3.0 3.3 3.6 v v i(vbat) input voltage on pin vbat 2.0 [4] 3.3 3.6 v standard port pins, reset, rtck i il low-state input current v i = 0 v; no pull-up - - 3 m a i ih high-state input current v i =v dd(3v3) ; no pull-down - - 3 m a i oz off-state output current v o =0v, v o =v dd(3v3) ; no pull-up/down --3 m a i latch i/o latch-up current - (0.5v dd(3v3) ) < v < (1.5v dd(3v3) ) t j < 125 c - - 100 ma v i input voltage pin con?gured to provide a digital function [5] [6] [7] 0 - 5.5 v v o output voltage output active 0 - v dd(3v3) v v ih high-state input voltage 2.0 - - v v il low-state input voltage - - 0.8 v v hys hysteresis voltage - 0.4 - v v oh high-state output voltage i oh = - 4ma [8] v dd(3v3) - 0.4 --v v ol low-state output voltage i ol = - 4ma [8] - - 0.4 v i oh high-state output current v oh =v dd(3v3) - 0.4 v [8] - 4--ma i ol low-state output current v ol = 0.4 v [8] 4--ma i ohs high-state short-circuit output current v oh =0v [9] -- - 45 ma i ols low-state short-circuit output current v ol =v dda [9] --50ma i pd pull-down current v i =5v [10] 10 50 150 m a i pu pull-up current v i =0v [11] - 15 - 50 - 85 m a v dd(3v3) 7 ma cclk = 70 mhz (other parameters as above) 41 ma i dd(pd) power-down mode supply current v dd(1v8) = 1.8 v, t a = +25 c 7 m a v dd(1v8) = 1.8 v, t a = +85 c m a
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 23 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers [1] typical ratings are not guaranteed. the values listed are at room temperature (+25 ?c), nominal supply voltages. [2] core and internal rail. [3] external rail. [4] the rtc typically fails when vbat drops below 1.6 v. [5] including voltage on outputs in 3-state mode. [6] v dd(3v3) supply voltages must be present. [7] 3-state outputs go into 3-state mode when v dd(3v3) is grounded. [8] accounts for 100 mv voltage drop in all supply lines. [9] only allowed for a short time period. [10] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. [11] applies to p1.25:16. [12] on pin vbat. [13] to v ss . i batpd power-down mode battery supply current [12] rtc clock = 32 khz (from rtxc pins), t a = +25 c v dd(1v8) = 1.8 v, vbat = 2.5 v - 7 m a v dd(1v8) = 1.8 v, vbat = 3.0 v - 8 m a i batact active mode battery supply current [12] cclk = 70 mhz, pclk = 17.5 mhz, pclk enabled to rtck, rtc clock = 32 khz (from rtxc pins), t a = +25 c v dd(1v8) = 1.8 v, vbat = 3.0 v m a i 2 c-bus pins v ih high-state input voltage 0.7v dd(3v3) --v v il low-state input voltage - - 0.3v dd(3v3) v v hys hysteresis voltage - 0.5v dd(3v3) -v v ol low-state output voltage i ols =3ma [8] - - 0.4 v i li input leakage current [13] v i =v dd(3v3) -24 m a v i = 5 v - 10 22 m a oscillator pins v i(xtal1) input voltage on pin xtal1 0 - 1.8 v v o(xtal2) output voltage on pin xtal2 0 - 1.8 v v i(rtxc1) input voltage on pin rtxc1 0 - 1.8 v v o(rtxc2) output voltage on pin rtxc2 0 - 1.8 v table 5: static characteristics continued t a = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 24 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers [1] conditions: v ssa =0v, v dda = 3.3 v. [2] the a/d is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 5 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 5 . [5] the offset error (e o ) is the absolute difference between the straight line which ?ts the actual curve and the straight line which ?ts the ideal curve. see figure 5 . [6] the gain error (e g ) is the relative difference in percent between the straight line ?tting the actual transfer curve after removing offset error, and the straight line which ?ts the ideal transfer curve. see figure 5 . [7] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated a/d and the ideal transfer curve. see figure 5 . table 6: adc static characteristics v dda = 2.5 v to 3.6 v; t a = - 40 c to +85 c unless otherwise speci?ed. adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] [3] -- 1 lsb e l(adj) integral non-linearity [1] [4] -- 2 lsb e o offset error [1] [5] -- 3 lsb e g gain error [1] [6] -- 0.5 % e t absolute error [1] [7] -- 4 lsb
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 25 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 5. a/d conversion characteristics 002aac046 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda - v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 26 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 9. dynamic characteristics [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] typical ratings are not guaranteed. the values listed are at room temperature (+25 ?c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. table 7: dynamic characteristics t a =0 c to +70 c for commercial applications, - 40 cto+85 c for industrial applications, v dd(1v8) ,v dd(3v3) over speci?ed ranges [1] symbol parameter conditions min typ [2] max unit external clock f osc oscillator frequency 10 - 25 mhz t cy(clk) clock cycle time 40 - 100 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns port pins (except p0.2 and p0.3) t r(o) output rise time - 10 - ns t f(o) output fall time - 10 - ns i 2 c-bus pins (p0.2 and p0.3) t f(o) output fall time v ih to v il 20 + 0.1 c b [3] --ns
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 27 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 10. package outline fig 6. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 28 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers fig 7. package outline sot187-2 (plcc44) unit a a 1 min. a 4 max. b p ey w v b references outline version european projection issue date iec jedec jeita mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot187-2 d (1) e (1) 16.66 16.51 h d h e 17.65 17.40 z d (1) max. z e (1) max. 2.16 b 1 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e d e e 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 ms-018 edr-7319 0 5 10 mm scale 99-12-27 01-11-14 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 29 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 11. abbreviations table 8: acronym list acronym description adc analog-to-digital converter apb advanced peripheral bus dcc debug communications channel dsp digital signal processor fifo first in, first out fiq fast interrupt request gpio general purpose input/output iap in-application programming irq interrupt request isp in-system programming pll phase-locked loop pwm pulse width modulator spi serial peripheral interface sram static random access memory ssp serial synchronous port uart universal asynchronous receiver/transmitter vic vectored interrupt controller
lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 30 of 32 philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 12. revision history table 9: revision history document id release date data sheet status change notice doc. number supersedes lpc2101_2102_2103_1 20060118 preliminary data sheet -- -
philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers lpc2101_02_03_1 ? koninklijke philips electronics n.v. 2006. all rights reserved. preliminary data sheet rev. 01 18 january 2006 31 of 32 13. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 14. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 15. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 16. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of koninklijke philips electronics n.v. 17. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2006 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 18 january 2006 document number: lpc2101_02_03_1 published in the netherlands philips semiconductors lpc2101/2102/2103 single-chip 16-bit/32-bit microcontrollers 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . 10 6.1 architectural overview. . . . . . . . . . . . . . . . . . . 10 6.2 on-chip ?ash program memory . . . . . . . . . . . 10 6.3 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 11 6.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 12 6.5.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12 6.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 12 6.7 fast general purpose parallel i/o . . . . . . . . . . 13 6.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.8 10-bit a/d converter . . . . . . . . . . . . . . . . . . . . 13 6.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.9 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.10 i 2 c-bus serial i/o controllers. . . . . . . . . . . . . . 14 6.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.11 spi serial i/o controller. . . . . . . . . . . . . . . . . . 14 6.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.12 ssp serial i/o controller . . . . . . . . . . . . . . . . . 15 6.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.13 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.14 general purpose 16-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.15 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 16 6.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.16 real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 17 6.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.17 system control . . . . . . . . . . . . . . . . . . . . . . . . 17 6.17.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 17 6.17.2 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.17.3 reset and wake-up timer . . . . . . . . . . . . . . . . 18 6.17.4 code security . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.17.5 external interrupt inputs . . . . . . . . . . . . . . . . . 18 6.17.6 memory mapping control . . . . . . . . . . . . . . . . 18 6.17.7 power control . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.17.8 apb bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.18 emulation and debugging. . . . . . . . . . . . . . . . 19 6.18.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 19 6.18.2 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 21 8 static characteristics . . . . . . . . . . . . . . . . . . . 22 9 dynamic characteristics . . . . . . . . . . . . . . . . . 26 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 27 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29 12 revision history . . . . . . . . . . . . . . . . . . . . . . . 30 13 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 31 14 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 16 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 17 contact information . . . . . . . . . . . . . . . . . . . . 31

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